1. Field of the Invention
The present invention relates to a debugging circuit and a method of controlling the debugging circuit, in particular, to a debugging circuit which controls the central processing unit during a preparation for debugging a predetermined program to be executed by the central processing unit and a method of controlling the central processing unit of the debugging circuit during the debugging preparation. This is a counterpart of and claims priority to Japanese Patent Application No. 2004-131063 filed on Apr. 27, 2004, which is herein incorporated by reference.
2. Description of the Related Art
In a central processing system incorporated in an electronics device, a central processing unit (hereinafter referred to as a “CPU”) executes a predetermined program and then controls a peripheral circuit such as a photographic image output circuit in the electronics device, as described in a Patent Document 1 (Japanese Patent Publication Laid-open No. 2000-276358).
FIG. 1 is a circuit block diagram for describing a debugging circuit in the central processing system of the related art. The debugging circuit in the central processing system has a CPU 1, an input-output circuit 2, a memory control circuit 3, a Read Only Memory 4 (ROM 4), a Random Access Memory 5 (RAM 5), a data bus 6, a memory bus 7, a reset signal input terminal 8, test access ports 100 which correspond to an interface of the Joint Test Action Group (hereinafter referred to as “JTAG interface”). The CPU 1 of the debugging circuit controls a peripheral circuit which is coupled to the input-output circuit 2. The peripheral circuit may be an external memory circuit or a photographic image output circuit.
The CPU 1 is reset when a reset signal HRESET is asserted. The reset of the CPU 1 is canceled when the reset signal HRESET is negated, and then the CPU 1 begins to operate in a normal operational mode. The CPU 1 reads out instruction codes which are stored in the ROM 4 and then executes a predetermined program in accordance with the instruction codes, just after the reset of the CPU 1 is canceled. Thereafter, the CPU 1 executes the predetermined program in accordance with the instruction codes without interruption or executes another program in accordance with instruction codes which are transferred from the external memory circuit in accordance with the instruction codes into the RAM 5.
In general, the CPU in the central processing system has a single step mode function of the program, a breaking function of the program, a reference/modification function to a control register in the CPU and a debugging function such as a reference/modification function to a memory circuit, in order to execute the debugging of the program with ease during a development of the program which is stored, for example, in the ROM 4 or the external memory circuit. Recently, in order to control the debugging function, the JTAG interface that can reduce the number of input/output signal lines is often used as shown in FIG. 1.
In order to realize the above-described debugging function, the CPU 1 as shown in FIG. 1, which has the JTAG interface, operates in the normal operational mode and a debugging operation mode. In the normal operational mode, the CPU 1 executes the program normally. In the debugging operation mode, the CPU 1 operates in accordance with debug data which are input to the CPU 1 through the JTAG interface in order to realize the debugging function. The switching between the normal operational mode and the debugging operation mode is controlled by command signals which are input to the CPU 1 through the JTAG interface.
FIG. 2 is a schematic circuit diagram for describing the JTAG interface. In the interface corresponding to the JTAG as shown in FIG. 2, the command signals are input to a control register 106 of the CPU 1 through the JTAG interface in accordance with a serial data transport protocol before the CPU 1 operates in the debugging operation mode. After the control register 106 receives the command signals, the CPU 1 asserts a debug acknowledge signal DBGACK and then suspends the normal operation mode to operate in the debugging operation mode. In addition, the debug acknowledge signal DBGACK is not particularly used in the debugging circuit of the central processing system shown in FIG. 1.
Before the CPU 1 operates in the debugging operation mode following the cancellation of the reset of the CPU 1, the CPU 1 prepares to debug the program so that the operation mode of the CPU 1 is switched from the normal operational mode to the debugging operation mode by the control from the JTAG interface. After the completion of the debugging preparation, the execution of the program stored in the ROM 4 or the external memory circuit is suspended. On the other hand, however, the debugging function of the CPU 1 is controlled through the JTAG interface in accordance with the serial data transport protocol in the debugging circuit of the central processing system. Therefore, it takes a long time to complete the debugging preparation from inputting the command signals to the test access ports 100 till inputting the command signals to the control register 106. As a result, it takes a long time from the cancellation of the reset of the CPU 1 till the completion of the debugging preparation. On such an occasion as this, the program stored in the ROM 4 or the external memory circuit may be executed by the CPU 1 during the debugging preparation. When the program is executed between the cancellation of the reset of the CPU 1 and the completion of the debugging preparation, the debugging operation of the CPU 1 may not be properly executed just after the cancellation of the reset of the CPU 1. Also, when the program is executed between the cancellation of the reset of the CPU 1 and the completion of the debugging preparation, the peripheral circuit controlled by the CPU 1 in the central processing system may operate unnecessarily. Furthermore, the debugging operation of the CPU 1 may be executed using a random-access memory such as a Static Random Access Memory (hereinafter referred to as “SRAM”) instead of the ROM 4. On such an occasion as this, at the beginning of the debugging operation, the program to be debugged is transported to the control register 106 of the CPU 1 through the JTAG interface, the program goes on to be transported from the control register 106 to the SRAM to be written in the SRAM, and then the CPU 1 reads out the program written in the SRAM to debug the program. In this case, the contents in the SRAM are indeterminate just after the cancellation of the reset of the CPU 1. Therefore, when the contents in the SRAM are executed between the cancellation of the reset of the CPU 1 and the completion of the debugging preparation, the CPU 1 may run out of control and then the peripheral circuit may execute an unpredictable operation.